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cywb0320abx-fdxi cywb0321abx-fdxi west bridge ? : arroyo usb and mass storage peripheral controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-57458 rev. *g revised july 22, 2013 west bridge ? : arroyo usb and mass storage peripheral controller features multimedia device support ? support next-gen sd, sdhc, sdio, and mmc+ simultaneous link to independent multimedia (slim ? ) architecture, enabling simultaneous and independent data paths between the processor and usb, and between the usb and mass storage. high speed usb at 480 mbps ? usb 2.0 compliant ? integrated usb 2.0 transceiver, smart serial interface engine ? 16 programmable endpoints flexible processor interface, which supports: ? spi (slave mode) interface ? multiplexing and nonmultiplexing address and data interface ? sram interface ? pseudo cram interface ? pseudo nand flash interface ? dma slave support ultra low power, 1.8 v core operation low power modes small footprint, 3.9 3.9 mm, 0.4 mm pitch, wlcsp supports i 2 c boot and processor boot clock input frequency ? 19.2 mhz ? 26 mhz applications cellular phones portable media players personal digital assistants portable navigation devices digital cameras pos terminals portable video recorders logic block diagram access control c control registers processor interface hi -speed usb 2.0 xcvr mass storage interface sd/mmc slim? s u p access control c control registers processor interface hi -speed usb 2.0 xcvr mass storage interface sd/mmc slim? s u p errata: for information on silicon errata, see ?errata? on page 50 and ?errata? on page 51. details include trigger conditions, devices affected, and proposed workaround.
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 2 of 53 contents functional overview ........................................................ 3 the slim architecture ................................................. 3 8051 microprocessor ... .............. .............. ........... ......... 3 configuration and status registers ............................. 3 processor interface (p-port) ........................................ 3 usb interface (u-port) ................................................ 3 clocking ....................................................................... 3 power domains ........................................................... 4 power modes .............................................................. 5 pin assignments .............................................................. 6 absolute maximum ratings .......................................... 13 operating conditions ..................................................... 13 dc characteristics ......................................................... 14 ac timing parameters ................................................... 16 p port interface ......................................................... 16 s port interface ac timing parameters .................... 43 reset and standby timing para meters ........ ............ 45 ordering information ...................................................... 47 ordering code definitions ......................................... 47 package diagram ............................................................ 48 acronyms ........................................................................ 49 document conventions ................................................. 49 units of measure ....................................................... 49 errata ............................................................................... 50 part numbers affected .............................................. 50 arroyo qualification status ........................................ 50 arroyo errata summary ......... .................................... 50 errata ............................................................................... 51 part numbers affected .............................................. 51 arroyo qualification status ........................................ 51 arroyo errata summary ......... .................................... 51 document history page ................................................. 52 sales, solutions, and legal information ...................... 53 worldwide sales and design s upport ......... .............. 53 products .................................................................... 53 psoc? solutions ...................................................... 53 cypress developer community ................................. 53 technical support ................. .................................... 53
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 3 of 53 functional overview the slim architecture the slim architecture enables thr ee different interfaces (p-port, s-port, and u-port) to connect to each other independently. with this architecture, a device using arroyo is connected to a pc through a usb, without disturbing any of the device functions. the device can still access mass storage when the pc is synchronizing with the main processor. the slim architecture enables new usage models, in which a pc accesses a mass storage device independent of the main processor, or enumerates access to both the mass storage and the main processor at the same time. you can do the following in a hands et using slim architecture: use the phone as a thumb drive. download media files to the phone with all the functionalities still available on the phone. use the same phone as a modem to connect the pc to the internet. 8051 microprocessor the 8051 microprocessor embedded in arroyo does basic transaction management for all tr ansactions between the p-port, s-port, and the u-port. the 8051 does not reside in the data path; it manages the path. the data path is optimized for performance. the 8051 executes firmware that supports sd, sdhc, sdio, and mmc+ devices at the s-port. configuration and status registers the west bridge ? arroyo device includes configuration and status registers that are accessible as memory-mapped registers through the processor interface. the configuration registers enable the system to s pecify some behaviors of arroyo. for example, it can mask certain status registers from raising an interrupt. the status registers c onvey the status of arroyo, such as the addresses of buffers for read operations. processor interface (p-port) communication with the external processor is realized through a dedicated processor interface. th is interface is configured to support different interface standards. this interface supports multiplexing and nonmultiplexing address or data bus in both synchronous and asynchronous pseudo cram-mapped, and nonmultiplexing address or data asynchronous sram-mapped memory accesses. the interface also can be configured to a pseudo nand interface to su pport the processor?s nand interface. in addition, this inte rface can be configured to support spi slave. asynchronous accesses can reach a bandwidth of up to 66.7 mbps. synchronous accesses can be performed at 33 mhz across 16 bits for up to 66.7 mbps bandwidth. the memory address is decoded to access any of the multiple endpoint buffers inside arroyo. these endpoints serve as buffers for data between each pair of ports; for example, between the processor port and the usb port. the processor writes and reads to these buffers through the memory interface. access to these buffers is contro lled by using a dma protocol or using an interrupt to the main processor. these two modes are configured by the external processor. as a dma slave, arroyo generates a dma request signal to notify the main processor that a specific buffer is ready to be read from or written to. the external processor monitors this signal and polls arroyo for the specific buf fers ready for a read or write operation. it then performs t he appropriate read or write operations on the buffer through the processor interface. as a result, the external processor only deals with the buffers to access a storage device connected to arroyo. in the interrupt mode, arroyo communicates important buffer status changes to the external processor using an interrupt signal. the external processor then polls arroyo for the specific buffers ready for read or write, and it performs the appropriate read or write operations through the processor interface. usb interface (u-port) in accordance with the usb 2. 0 specification, arroyo can operate in both full speed and high speed usb modes. the usb interface consists of the usb transceiver. the usb interface can access and be accessed by both the p-port and the s-port. the arroyo usb interface supports programmable control/bulk/interrupt/isochronous endpoints. mass storage support (s-port) the s-port may be configured to support the following: next-gen sd/sdio/emmc+ port when arroyo is configured through firmware to support sd/sdio/mmc+, this interface supports the following: sd memory card specification - part 1, physical layer specification, sd group, version 2.0, may 9, 2006. sd memory card specification - part 1, physical layer specification, sd group, ve rsion 1.10, october 15, 2004. sd specifications - part e1 sd io specification, version 1.10, august 18, 2004. the multimedia card system specification, mmca technical committee, version 4.1. west bridge arroyo supports 1-bit and 4-bit sd and sdio cards; 1-bit, 4-bit, and 8-bit mmc; mmc+ cards. for the sd, sdio, and mmc/mmc plus, this block supports one card for one physical bus interface. arroyo supports sd commands including the multisector program command that is handled by api clocking arroyo enables connection of an external clock at the xtalin pin. the power supply level at the crystal supply xvddq determines whether a crystal or a clock is provided. if xvddq is detected to be 1.8 v, arroyo assumes that a clock input is provided. for a crystal to be connected, xvddq must be 3.3 v. note clock inputs at 3.3 v level are not supported. the 81-pin wlcsp supports 19.2 mhz and 26 mhz external clock input. the crystal or clock frequency selection is shown in table 1 on page 4 .
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 4 of 53 the xtalin frequency is independent of the clock and data rate of the 8051 microprocessor or any of the device interfaces (including p-port and s-port). the internal pll applies the proper clock multiply option depending on the input frequency. for applications that use an external clock source to drive xtalin, the xtalout, pin must be left floating. the external clock source must also stop high or low and not toggle, to achieve the lowest possible current consumption. the requirements for an external clock source are shown in table 3 . arroyo has an on-chip oscillator circuit that uses an external 26 mhz (150 ppm) crystal with the following characteristics: parallel resonant fundamental mode 1 mw drive level 12 pf (5% tolerance) load capacitors 150 ppm note cywb0321abx-fdxi does not support crystal. figure 1. crystal configuration power domains arroyo has multiple power domains that serve different purposes within the chip. vddq: this refers to a group of five independent supply domains for the digital i/os. the nominal voltage level on these supplies are 1.8 v, 2.5 v, or 3.3 v. specifically, the four separate i/o power domains are: pvddq ? p-port processor interface i/o ssvddq ? s-port sd interface i/o gvddq ? other miscellaneous i/o astoria xtalin xtalout pll 12pf 12pf xtal * 12 pf capacitor values assumes a trace capacitance of 3 pf per side on a four layer fr4 pca arroyo table 1. cywb0320abx-fdxi clock selection xtalslc freq crystal/clock na 26 mhz clock or crystal table 2. cywb0321abx-fdxi clock selection xtalslc freq crystal/clock 0 19.2 mhz clock 126 mhzclock table 3. external clock requirements parameter description specification unit min max vn (avddq) supply voltage noise at frequencies < 50 mhz ? 20 mv p-p pn_100 input phase noise at 100 hz ? ?75 dbc/hz pn_1k input phase noise at 1 khz offset ? ?104 dbc/hz pn_10k input phase noise at 10 khz offset ? ?120 dbc/hz pn_100k input phase noise at 100 khz offset ? ?128 dbc/hz pn_1m input phase noise at 1 mhz offset ? ?130 dbc/hz duty cycle 30 70 % maximum frequency deviation ? 150 ppm overshoot ?3% undershoot ??3%
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 5 of 53 uvddq: this is the 3.3 v nominal supply for the usb i/o and some analog circuits. it also supplies power to the usb transceiver. vdd: this is the supply voltage for the logic core. the nominal supply voltage level is 1.8 v. this supplies the core logic circuits. the same supply must also be used for avddq. avddq: this is the 1.8 v supply for pll and usb serializer analog components. the same supply must also be used for vdd. maximum permitted noise on avddq is 20 mv p-p. xvddq: this is the clock i/o supply; 3.3 v for xtal or 1.8 v for an external clock. noise guideline for all supplies except avddq is maximum 100 mv p-p. all i/o s upplies of arroyo must be on when a system is active even if arroyo is not in use. the core vdd can also be deactivated at any time to preserve power, provided there is a minimum impedance of 1 k ? between the vdd pin and ground. all i/os tristate when the core is disabled. figure 2. arroyo power supply domains power supply sequence the power supplies are independently sequenced without damaging the part. all power supplies must be up and stable before the device operates. if the supplies are not stable, the remaining domains are in low power (standby) state. power modes in addition to the normal operating mode, arroyo contains several low power states when normal operation is not required. normal mode normal mode is the mode in which arroyo is fully functional. in this mode data transfer functions described in this document are performed. suspend mode this mode is entered internally by 8051 (external processor only initiates entry into this mode through mailbox commands). this mode is exited by the d+ bus going low, gpio[0] going to a pre-determined state or by asserting ce# low. in arroyo?s suspend mode: the clocks are shut off. all i/os maintain their previous state. core power supply must be retained. the states of the configuration registers, endpoint buffers, and the program ram are maintained. all transactions must be complete before arroyo enters suspend mode (state of outstanding transactions are not preserved). the firmware resumes its operation from where it was suspended, since the program counter is not reset. only inputs that are sensed are reset#, gpio[0]/sd_cd, gpio[1], sd_d3, d+, and ce#. the last three are wake up sources (each can be individually enabled or disabled). hard reset can be performed by asserting the reset# input, and arroyo is initialized. standby mode standby mode is a low power state. this is the lowest power mode of arroyo while still maintaining external supply levels. this mode is entered through deassertion of the wakeup input pin or through internal register settings. to leave this mode, assert wakeup, ce#, and reset#; and change the state of gpio[0]/sd_cd, gpio[1], or sd_d3. in this mode all configuration register settings and program ram contents are preserved. however, data in the buffers or other parts of the data path, if any, is not guaranteed in values. therefore, the external processo r must ensure that the required data is read before putting arroyo into the standby mode. in the standby mode: the program counter is reset on waking up from standby mode. all outputs are tristated and i/o is placed in input only configuration. values of i/os in standby mode are listed in the pin assignments table. core power supply must be retained. hard reset can be performed by asserting the reset# input, and arroyo is initialized. pll is disabled. core power down mode the core power supply vdd is powered down in this state. avddq is tied to the same supply as vdd and is hence, also powered down. neither the endpoint buffers, configuration registers nor program ram maintain state. it is required that all vddq power supplies (except avddq) are on and not power downer down in this mode. when uvddq is powered down, d+/d? can?t be driven by external device. the core power down mode has two power down options: core only power down ? vdd power down. core and usb power down ? vdd and uvddq are both powered down. in these power down options, the endpoint buffers, configuration registers, or the program ram do not maintain state. it is necessary to reload the firmware on exiting from this mode. it is required that all vddq power supplies are on and not powered down in this mode. usb-io d-core i/o uvddq vdd d+ d- *vddq
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 6 of 53 pin assignments table 4. cywb0320abx-fdxi wlcsp package pin assignments pin name pin description power domain p-port ball # pseudo cram interface i/o sram interface [1] i/o adm (address/data multiplexing) i/o pnand i/o j3 ce# i ce# i ce# i ce# i ce# pvddq vgnd e2 a7 i a7 i external pull up i a7 => 1:sbd a7 => 0: lbd ia7 h1 a6 i a6 i sda i/o sda i/o a6 or sda f2 a5 i a5 i scl i/o scl i/o a5 or scl g2 a4 i a4 i external pull up i wp# i a4 or wp# j1 a3 i a3 i external pull low i external pull low i a3 h2 a2 i a2 i external pull up i external pull low i a2 j2 a1 i a1 i external pull up i r/b# o a1 or r/b# h3 a0 i a0 i external pull up i cle i a0 or cle f3 dq[15] i/o dq[15] i/o ad[15] i/o i/o[15] i/o d15, ad15, or io15 j4 dq[14] i/o dq[14] i/o ad[14] i/o i/o[14] i/o d14, ad14, or io14 h4 dq[13] i/o dq[13] i/o ad[13] i/o i/o[13] i/o d13, ad13, or io13 g4 dq[12] i/o dq[12] i/o ad[12] i/o i/o[12] i/o d12, ad12, or io12 j5 dq[11] i/o dq[11] i/o ad[11] i/o i/o[11] i/o d11, ad11, or io11 h5 dq[10] i/o dq[10] i/o ad[10] i/o i/o[10] i/o d10, ad10, or io10 j6 dq[9] i/o dq[9] i/o ad[9] i/o i/o[9] i/o d9, ad9, or io9 g6 dq[8] i/o dq[8] i/o ad[8 i/o i/o[8] i/o d8, ad8, or io8 h6 dq[7] i/o dq[7] i/o ad[7] i/o i/o[7] i/o d7, ad7, or io7 j7 dq[6] i/o dq[6] i/o ad[6] i/o i/o[6] i/o d6, ad6, or io6 f6 dq[5] i/o dq[5] i/o ad[5] i/o i/o[5] i/o d5, ad5, or io5 j8 dq[4] i/o dq[4] i/o ad[4] i/o i/o[4] i/o d4, ad4, or io4 h7 dq[3] i/o dq[3] i/o ad[3] i/o i/o[3] i/o d3, ad3, or io3 g7 dq[2] i/o dq[2] i/o ad[2] i/o i/o[2] i/o d2, ad2, or io2 h8 dq[1] i/o dq[1] i/o ad[1] i/o i/o[1] i/o d1, ad1, or io1 h9 dq[0] i/o dq[0] i/o ad[0] i/o i/o[0] i/o d0i, ad0, or io0 g8 adv# i i adv# i ale i address valid f8 oe# i oe# i oe# i re# i output enable g9 we# i iwe# iwe# iwe# int a7 int# o o int# o int# o int request gvddq vgnd d6 drq o o drq o drq o dma request c6 dack i i dack i dack i dma ack u-port d9 d+ i/o/z usb d+ uvddq uvssq e9 d? i/o/z usb d? d7 nc i/o/z left floating e7 nc i/o/z left floating note 1. errata: when arroyo is configured to use sram fo r p-port interface, oe should be asserted simultaneously with ce. if this is not possi ble, oe should be asserted prior to ce. otherwise, data can be dropped when external proc essor reads the arroyo through sram interface. for more informati on, see the ?errata? on page 50 and ?errata? on page 51.
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 7 of 53 s-port s-port interface i/o c4 sd_d[7] i/o sd data or gpio ssvddq vgnd a2 sd_d[6] i/o sd data or gpio b3 sd_d[5] i/o sd data or gpio c5 sd_d[4] i/o sd data or gpio b4 sd_d[3] i/o sd data or gpio a4 sd_d[2] i/o sd data or gpio b5 sd_d[1] i/o sd data or gpio a5 sd_d[0] i/o sd data or gpio a3 sd_clk o sd clock or gpio a1 sd_cmd i/o sd cmd or gpio e1 pb[7] (gpio) i/o gpioi d1 pb[6] (gpio) i/o gpioi d2 pb[5] (gpio) i/o gpioi c1 pb[4] (gpio) i/o gpioi c2 pb[3] (gpio) i/o gpioi d3 pb[2] (gpio) i/o gpioi b1 pb[1] (gpio) i/o gpioi b2 pb[0] (gpio) i/o gpioi g1 testtree otest mode f1 scan (ext pull-low) i test mode (ext pull-low) other a6 sd_cd i sd cd gvddq vgnd b7 reset# i reset e5 wakeup i wake up signal conf c7 test[2] i test cfg 2 gvddq vgnd e6 test[1] i test cfg 1 a8 test[0] i test cfg 0 clk b9 xtalin i clock in xvddq vgnd a9 xtalout o clock out power f4, j9 pvddq power processor i/f vdd e8 uvddq power usbvdd d5 ssvddq power sdio vdd b6 gvddq power misc i/o vdd c8 avddq power analog vdd d8 xvddq power crystal vdd e4, g5, f7, f9 vdd power core vdd c9 uvssq power usb gnd b8 avssq power analog gnd c3, d4, e3, f5, g3 vgnd power core gnd table 4. cywb0320abx-fdxi wlcsp package pin assignments (continued) pin name pin description power domain
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 8 of 53 table 5. cywb0321abx-fdxi wlcsp package pin assignments pin name pin description power domain p-port ball # pnand i/o spi [2] i/o j2 ext pull low i sck i clock pvddq vgnd j4 ce# i ss# i ce# or spi slave select g5 sda i/o sda i/o i2c data h2 scl i/o scl i/o i2c clock j1 wp# i ext pull up i pnand wp h3 a[3] (ext pull low) i a[3] (ext pull up) i a[3] f5 a[2] (ext pull low) i a[2] (ext pull low) i a[2] j3 rb# o ext pull up i pnand r/b# h4 cle i ext pull up i pnand cle j6 i/o[7] i/o ext pull up i io7 h6 i/o[6] i/o ext pull up i io6 j7 i/o[5] i/o ext pull up i io5 j8 i/o[4] i/o ext pull up i io4 h7 i/o[3] i/o ext pull up i io3 g7 i/o[2] i/o ext pull up i io2 h8 i/o[1] i/o sdo o io1 or spi sdo h9 i/o[0] i/o sdi i io0 or spi sdi g8 ale i ext pull up i address valid f8 re# i ext pull up i output enable g9 we# i ext pull up i we# int a7 int# o sint# o int request gvddq vgnd u-port d9 d+ i/o/z usb d+ uvddq uvssq e9 d? i/o/z usb d? d7 nc i/o/z left floating e7 nc i/o/z left floating note 2. errata: when arroyo is configured to use spi for processor-port (p-port) interface, transfers from u-port to p-port may intermittently fail after wakeup from standby mode. workaround for this problem is added in sdk version 1.0 or later. for more information, see the ?errata? on page 50 and ?errata? on page 51.
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 9 of 53 s-port ball # sdio i/o gpio only configuration i/o b2 sd_d[7] i/o pd[7] (gpio) i/o sd data or gpio ssvddq vgnd a2 sd_d[6] i/o pd[6] (gpio) i/o sd data or gpio c3 sd_d[5] i/o pd[5] (gpio) i/o sd data or gpio b3 sd_d[4] i/o pd[4] (gpio) i/o sd data or gpio b4 sd_d[3] i/o pd[3] (gpio) i/o sd data or gpio c4 sd_d[2] i/o pd[2] (gpio) i/o sd data or gpio c5 sd_d[1] i/o pd[1] (gpio) i/o sd data or gpio b5 sd_d[0] i/o pd[0] (gpio) i/o sd data or gpio a3 sd_clk o pc-7 (gpio) i/o sd clock d4 sd_cmd i/o pc-3 (gpio) i/o sd cmd a1 sd_pow o pc-6 (gpio) i/o sd pow a5 sd_wp i unused i sd wp, gpio e2 sd_rsv i/o pb[7] (gpio) i/o connect to ssvddq with 10k pull up resister ssvddq vgnd d1 sd_rsv i/o pb[6] (gpio) i/o e3 sd_rsv i/o pb[5] (gpio) i/o d2 sd_rsv i/o pb[4] (gpio) i/o c1 sd_rsv i/o pb[3] (gpio) i/o d3 sd_rsv i/o pb[2] (gpio) i/o c2 sd_rsv i/o pb[1] (gpio) i/o b1 sd_rsv i/o pb[0] (gpio) i/o g2 sd_rsv i unused i f2 nc o pa-7 (gpio) i/o left floating g3 nc o pc-0 (gpio) i/o h1 nc o n/c o e1 nc o n/c o f3 nc o pa-5 (gpio) i/o g4 nc o pa-6 (gpio) i/o g1 nc o pc-2 (gpio) i/o other b7 resetout o resetout o resetout gvddq vgnd b6 pc-5 (gpio[1]) i/o o pc-5 (gpio[1]) i/o gpio, sd2 cd4 a6 pc-4 (gpio[0]) or sd_cd i/o i o pc-4 (gpio[0]) i/o gpio, sd1 cd c7 reset# i reset d6 wakeup i wake up signal conf a9 xtalslc clock select gvddq vgnd a8 test[2] i test cfg 2 f7 test[1] test cfg 1 d8 test[0] test cfg 0 clk b9 xtalin i clock in vgnd table 5. cywb0321abx-fdxi wlcsp package pin assignments (continued) pin name pin description power domain
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 10 of 53 power h5, j9 pvddq power processor i/f vdd f1 ssvddq power sdio vdd e8 uvddq power usb vdd a4 ssvddq power sdio vdd c6 gvddq power misc i/o vdd c8 avddq power analog vdd e5, f4, f6, f9 vdd power core vdd c9 uvssq power usb gnd b8 avssq power analog gnd d5, e4, e6, g6, j5 vgnd power core gnd table 5. cywb0321abx-fdxi wlcsp package pin assignments (continued) pin name pin description power domain
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 11 of 53 figure 3. cywb0320abx-fdxi wlcsp ball map - top view 123456789 a sd_cmd sd_d[6] sd_clk sd_d[2] sd_d[0] gpio[0] int# test[0] xtalout a b nand_io[1] nand_io[0] sd_d[5] sd_d[3] sd_d[1] gvddq reset# avssq xtalin b c nand_io[4] nand_io[3] vgnd sd_d[7] sd_d[4] dack# test[2] avddq uv ssq c d nand_io[6] nand_io[5] nand_io[2] vgnd ssvddq drq# nc xvddq d+ d e nand_io[7] a[7] vgnd vdd wakeup test[1] nc uv ddq d- e f scan a[5] dq[15] pvddq vgnd dq[5] v dd oe# v dd f g testtree a [4] vgnd dq[12] vdd dq[8] dq[2] adv# we# g h a[6] a[2] a[0] dq[13] dq[10] dq[7] dq[3] dq[1] dq[0] h j a[3] a[1] ce# dq[14] dq[11] dq[9] dq[6] dq[4] pvddq j 123456789 xvddq ssvddq v dd/avddq vgnd/avssq pvddq power domain key uvddq uvssq gvddq
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 12 of 53 figure 4. cywb0321abx-fdxi wlcsp ball map ? top view 123456789 a sd_pow sd_d[6] sd_clk ssvddq sd_wp gpio[0] int# test[2] xtalslc a b sd_rsv sd_d[7] sd_d[4] sd_d[3] sd_d[0] gpio[1] resetout avssq xtalin b c sd_rsv sd_rsv sd_d[5] sd_d[2] sd_d[1] gvddq reset# avddq uv ssq c d sd_rsv sd_rsv sd_rsv sd_cmd vgnd wakeup nc test[0] d+ d e nc sd_rsv sd_rsv vgnd vdd v gnd nc uv ddq d- e f ssv ddq nc nc v dd a [2] v dd test[1] re# v dd f g nc sd_rsv nc nc sda vgnd io[2] a le we# g h nc scl a[3] cle pvddq io[6] io[3] io[1] io[0] h j wp# pull-low r/b# ce# vgnd io[7] io[5] io[4] pv ddq j 123456789 ssvddq v dd/avddq vgnd/avssq pvddq power domain key uvddq uvssq gvddq
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 13 of 53 absolute maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature ................ ............... ?65 c to +150 c ambient temperature with power supplied (industrial) ........ ............... ?40 c to +85 c supply voltage to ground potential vdd, avddq ..............................................?0.5 v to +2.0 v gvddq, pvddq, ssvddq, uvddq, and xvddq ..................................?0.5 v to +4.0 v dc input voltage to any input pin .................1.89 v to 3.6 v (depends on i/o supply voltage. inputs are not overvoltage tolerant.) dc voltage applied to outputs in high z state .................. ?0.5 v to vddq + 0.5 v static discharge voltage (esd) from jesd22-a114 ...................................... > 2000 v latch up current ..................................................... > 200 ma maximum output short circuit current for all i/o configurations. (vout = 0 v) .................... ?100 ma operating conditions t a (ambient temperature under bias) industrial .................................................... ?40 c to +85 c vdd, avddq supply voltage ...... .............. .....1.7 v to 1.9 v uvddq supply voltage ...................................3.0 v to 3.6 v pvddq, gvddq, ssvddq supply voltage .................................................1.7 v to 3.6 v xvddq (crystal i/o) supply voltage ..............3.0 v to 3.6 v xvddq (ext. clock i/o) supply voltage .........1.7 v to 1.9 v
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 14 of 53 dc characteristics table 6. dc specifications for all voltage supplies parameter description conditions min typ max unit vdd core voltage supply 1.7 1.8 1.9 v avddq analog voltage supply 1.7 1.8 1.9 v xvddq crystal voltage supply 3.0 3.3 3.6 v xvddq clock voltage supply 1.7 1.8 1.9 v pvddq [3] processor interface i/o 1.7 1.8, 2.5, 3.3 3.6 v gvddq [3] miscellaneous i/o voltage supply 1.7 1.8, 2.5, 3.3 3.6 v ssvddq [3, 4] s-port sd i/o voltage supply 1.7 1.8, 2.5, 3.3 3.6 v uvddq [5] usb voltage supply 3.0 3.3 3.6 v v ih1 [6] input high voltage 1 all ports except usb, 2.0 v < v cc < 3.6 v 0.625 v cc ?v cc + 0.3 v v ih2 [6] input high voltage 2 all ports except usb, 1.7 v < v cc < 2.0 v v cc ? 0.4 ? v cc + 0.3 v il input low voltage ?0.3 ? 0.25 v cc v v oh output high voltage i oh (max) = ?0.1 ma 0.9 v cc ??v v ol output low voltage i ol (min) = 0.1 ma ? 0.1 v cc v i ix input leakage current all i/o signals held at vddq ?1 ? 1 ? a i oz output leakage current all i/o signals held at vddq ?1 ? 1 ? a i cc core operating current of core voltage supply (vdd) and analog voltage supply (avddq) wlcsp package, outputs tristated ? ? 115 ma i cc crystal operating current of crystal voltage supply (xvddq) [7] wlcsp package ? ? n/a i cc usb operating current of usb voltage supply (uvddq) [7] operating and terminated for high speed mode ??25ma i sb1 total standby current of arroyo when device is in suspend mode 1. *vddq = 3.3 v nominal (3.0?3.6 v) 2. outputs and bidirs high or floating [7] 3. xtalout floating 4. d+ floating, d? grounded 5. device in suspend mode 25 c tbd tbd tbd 85 c tbd tbd tbd notes 3. interfaces with a voltage range are adjustable with respect to the i/o voltage and supports multiple i/o voltages. 4. the ssvddq i/o voltage can be dynamically changed (for example, from high range to lo w range) as long as the supply voltage u ndershoot does not surpass the lower minimum voltage limit. ssvddq and snvddq levels for sd modes: 2.0 v ? 3.6 v, mmc modes: 1.7 v ? 3.6 v. 5. when u-port is in a disabled state, uv ddq can go down to 2.4 v, provided uvddq is still the highest supply voltage level. 6. v cc = pertinent vddq value. 7. the outputs and bidirs that are forced low in standby mode can increase i/o supply standby current beyond specified value. active current conditions: -uvddq: usb transmitting 50% of the time, receiving 50% of the time. -pvddq/snvddq/ssvddq/gvddq: active current depends on i/o activity, bus load and supply level.
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 15 of 53 i sb2 total standby current of arroyo when device is in standby mode 1. *vddq = 3.3 v nominal (3.0?3.6 v) 2. outputs and bidirs high or floating [7] 3. xtalout floating 4. d+ floating, d? grounded 25 c ? ? 52 ? a 85 c ? ? 450 ? a i sb3 total standby current of arroyo when device is in core power down mode 1. outputs and bidirs high or floating [7] 2. xtalout floating 3. d+ floating, d? grounded 4. core powered down 25 c ? ? 28 ? a 85 c ? ? 139 ? a table 6. dc specifications for all voltage supplies (continued) parameter description conditions min typ max unit table 7. capacitance parameter description conditions typ max unit c in input pin capacitance, except d+/d? ta = 25 c, f = 1 mhz, v cc = v ccio ?9pf input pin capacitance, d+/d? ? 15 c out output pin capacitance ? 10 pf
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 16 of 53 ac timing parameters p port interface pcram non multiplexing asynchronous mode table 8. asynchronous mode timing parameters parameter description min max unit read timing parameters interface bandwidth (mbps) ? 66.7 mbps t aa address to data valid ? 30 ns t oh data output hold from address change 3 ? ns t ea chip enable to data valid ? 30 ns t aadv adv# to data valid access time ? 30 ns t avs address valid to adv# high 5 ? ns t avh adv# high to address hold 2 [8] ?ns t cvs ce# low setup time to adv# high 5 ? ns t vph adv# high time 15 [9] ?ns t vp adv# pulse width low 7.5 ? ns t oe oe# low to data valid ? 22.5 ns t olz oe# low to low z 3 ? ns t ohz oe# high to high z 0 22.5 ns t lz ce# low to low z 3 ? ns t hz ce# high to high z ? 22.5 ns write timing parameters t cw ce# low to write end 30 ? ns t aw address valid to write end 30 ? ns t as address setup to write start 0 ? ns t advs adv# setup to write start 0 ? ns t wp we# pulse width 22 ? ns t wph we# high time 10 ? ns t cph ce# high time 10 ? ns t avs address valid to adv# high 5 ? ns t avh adv# high to address hold 2 [8] ?ns t cvs ce# low setup time to adv# high 5 ? ns t vph adv# high time 15 [9] ?ns t vp adv# pulse width low 7.5 ? ns t vs adv# low to end of write 30 ? ns t dw data setup to write end 18 ? ns t dh data hold from write end 0 ? ns t whz write to dq high z output ? 22.5 ns t ow end of write to low z output 3 ? ns notes 8. in applications where back-to-back accesses are not performed on different endpoint addresses, the minimum t avh spec. can be relaxed to 0 ns. 9. in applications where access cycle time is at least 60 ns, t vph can be relaxed to 12 ns.
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 17 of 53 figure 5. non multip lexing asynchronous pseudo cram mode single read timing parameters a adv# ce# oe# r/w# dq taa tea toe tolz tohz tlz thz valid address high-z tvph tavs tavh tvp valid output taadv toh tcvs figure 6. non multiplexing asynchronous pseudo cram mode back to back read timing parameters a adv# ce# oe# we# dq taa tea tohz tlz thz high-z tvph tavs tavh tvp taadv valid address valid address valid output valid output
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 18 of 53 figure 7. non multiplexing asynchronous pseudo cram mode back to back write timing parameters a adv# ce# oe# we# dq_in high-z tvph tavs tavh tvp valid address valid input valid input tdw tdh dq_out tvs tas twhz tlz valid address taw tcw tow twph twp tadvs tcph figure 8. non multiplexing asynchronous pseu do cram mode read to write timing parameters a adv# ce# oe# we# dq_in high-z tvph tavs tavh tvp valid address valid input valid input tdw tdh dq_out tvs tas twhz valid address taw tow twp taa toe tolz tlz high-z tvph tavs tavh tvp taadv valid address valid output tohz tea
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 19 of 53 figure 9. non multiplexing asynchronous pseudo cram mode write to read timing parameters a adv# ce# oe# we# dq_in tavs tavh tvp valid address valid input tdw tdh dq_out tvs tas twhz taw twp taa toe tolz tavs tavh tvp taadv valid address valid output
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 20 of 53 address data multiplexing asynchronous mode table 9. address data multiplexing asynchronous mode timing parameters parameter description min max unit read timing parameters interface bandwidth ? 50 mbps t aa address to data valid ? 30 ns t ea chip enable access time ? 30 ns t aadv adv# to data valid access time ? 30 ns t avs address valid to adv# high 5 ? ns t avh adv# high to address hold 2 ? ns t cvs ce# low setup time to adv# high 5 ? ns t vph adv# high time 15 ? ns t vp adv# pulse width low 7.5 ? ns t avdoe adv# high to oe# low 0 ? ns t oe oe# low to data valid ? 22.5 ns t olz oe# low to low z 3 ? ns t ohz oe# high to high z ? 22.5 ns t lz ce# low to low z 3 ? ns t hz ce# high to high z ? 22.5 ns write timing parameters t cw ce# low to write end 30 ? ns t aw address valid to write end 30 ? ns t avdwe adv# high to write start 0 ? ns t wp we# pulse width 22 ? ns t avs address valid to adv# high 5 ? ns t avh adv# high to address hold 2 ? ns t cvs ce# low setup time to adv# high 5 ? ns t vph adv# high time 15 ? ns t vp adv# pulse width low 7.5 ? ns t vs adv# low to end of write 30 ? ns t ds data setup to write end 18 ? ns t dh data hold from write end 0 ? ns
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 21 of 53 figure 10. address data multiplexing asynchronous single read timing parameters a<7:0>/ dq<15:0> adv# ce# oe# we# valid data taa toe tolz tohz thz high-z tvph tavs tavh tvp taadv valid address tea tlz high-z logic high tavdoe tcvs figure 11. address data multiplexing asynchronous single write timing parameters a<7:0>/ dq<15:0> adv# ce# we# taw twp tvph tavs tavh tvp valid address tcw high-z tavdwe valid input tds tdh t v s tcvs
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 22 of 53 asynchronous sram mode timing parameters table 10. asynchronous sram mode timing parameters parameter description min max unit interface bandwidth (mbps) ? 66.7 mbps read timing parameters t rc read cycle time 30 ? ns t aa address to data valid ? 30 ns t oh data output hold from address change 3 ? ns t ea chip enable to data valid ? 30 ns t oe oe# low to data valid ? 22.5 ns t olz oe# low to low z 3 ? ns t ohz oe# high to high z 0 22.5 ns t lz ce# low to low z 3 ? ns t hz ce# high to high z ? 22.5 ns write timing parameters t wc write cycle time 30 ? ns t cw ce# low to write end 30 ? ns t aw address valid to we# end 30 ? ns t as address setup to we# or ce# start 0 ? ns t ah address hold time from we# or ce# e nd for pcram to sram changes (astoria is default in pcram mode after reset. this timing is the requirement for the first time to access the p-port interface configur ation register to change the astoria to psram mode) 2?ns address hold time from we# or ce# end for psram mode 0 ? t wp we# pulse width 22 ? ns t wph we# high time 10 ? ns t cph ce# high time 10 ? ns t ds data setup to write end 18 ? ns t dh data hold from write end 0 ? ns t whz write to dq high z output ? 22.5 ns t ow end of write to low z output 3 ? ns t dpw drq# pulse width 110 ? ns
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 23 of 53 figure 12. non multiplexing asynchronous sram read timing parameters [10] trc taa toh trc tea toe tolz tohz thz tlz address data out dat a valid previous data valid address ce# oe# data out dat a valid high impedance high impedance endpoint read ? address transition controlled timing (oe# is asserted ) oe # controlled timing note 10. errata: when arroyo is configured to use sram for p-port interf ace, oe should be asserted simultaneously with ce. if this is no t possible, oe should be asserted prior to ce. otherwise, data can be dropped when external proc essor reads the arroyo through sram interface. for more informati on, see the ?errata? on page 50 and ?errata? on page 51.
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 24 of 53 figure 13. non multiplexing asynchronous sram write timing (we# and ce# controlled) write cycle 2 ce# controlled , oe# high during w rite twc tcw taw tas tah tds tdh twhz valid data address data i/o twp ce# we# oe # write cycle 1 we# controlled, oe# high during write twph valid data twc tcw taw tas tah tds tdh twhz valid data address data i/o twp ce# we# oe # tcph valid data
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 25 of 53 pseudo nand (pnand) mode figure 14. non multiplexing asynchronous sram write timing (we# controlled, oe# low) twc tcw taw tas tah tds tdh valid data ce# we# data i/o twp tow twhz write cycle 3 we# controlled. oe# low table 11. pnand mode parameters parameter description min max unit t adl address to data loading time non lna mode register write 100 ? ns non lna mode ep write 100 ? ns lna mode 450 ? ns t alh ale hold time 5?ns t als ale setup time 15 ? ns t ar ale to re# delay 10 ? ns t bers block erase time mcu/s-port nand dependent t cea ce# access time ? 35 ns t ch ce# hold time 5?ns t chz ce# high to o/p hi-z ? 40 ns t clh cle hold time 5?ns t clr cle to re# time 10 ? ns t cls cle setup time 15 ? ns t cs ce# setup time 20 ? ns t dh data hold time 5?ns t ds data setup time 15 ? ns t oh data output hold time 15 ? ns
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 26 of 53 t prog program time for lna mode depends on mcu/s-port/nand ns program time for register write in non lna mode 130 ? ns program time for ep write in non lna mode 130 ? ns t r busy duration during non lna register read using page read 130 ? ns busy duration during non lna ep read using page read 130 ? ns busy duration during ln a page read (sbd/sld) depends on mcu/s-port/nand ns t rc read cycle time (vfbga package) 30 ? ns read cycle time (wlcsp package) 33 ? t rea re# for register access time ? 30 ns re# for ep access time ? 30 ns t reh re# high hold time 10 ? ns t rhw re# high to we low 40 ? ns t rhz re# high to output hi-z ? 40 ns t rp re# pulse width 15 ? ns t rr ready to re low 20 ? ns t rst device reset time depends on mcu/s-port/nand ns t wb we# high to busy ? 100 ns t wc write cycle time (vfbga package) 30 ? ns write cycle time (wlcsp package) 33 ? t wh we# high hold time 10 ? ns t whr we# high to re low in non lna mode 30 ? ns we# high to re low in lna mode 450 ? ns t wp we# pulse width 15 ? ns table 11. pnand mode parameters (continued) parameter description min max unit
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 27 of 53 figure 15. pnand mode command latch cycle cle ce# we# ale i/ox tcls tclh tcs tch twp tals talh tds tdh command figure 16. pnand mode address latch cycle tcls tcs twc twc twc twc twp twp twp twp tals tals tals tals talh twh twh twh twh tdh t a l s tds tds tdh tds tdh td s tdh tds tdh talh talh talh talh cle ce# we# ale i/ox col.add2 row.add1 row.add2 row.add3 col.add1
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 28 of 53 figure 17. pnand mode input data latch cycle twp twp twp twh tds tds tds tdh tdh tdh din 0 din 1 din final twc tals tclh tch cle ce# ale we# i/ox figure 18. pnand mode serial access cycle after read treh trr trc trea trea trea trhz dout dout dout trhz toh tcea tchz toh ce# re# i/ox r/ b #
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 29 of 53 figure 19. pnand mode status read cycle tcls tclr tcs twp tds tdh trea twhr tcea tir trhz tchz toh toh 70h status output tclh cle ce# we # re# i/ox figure 20. pnand lbd read operation tr tr r twc trc trhz tar twb busy tclr 00h col add1 col add2 row ad d1 row add2 row add3 30h dout n dout n+1 dout m column address row address cle ce# we# ale re# i/ox r/b# trp
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 30 of 53 figure 21. pnand sbd read operation tr trr twc trc trhz twb busy 00h, 01h, or *50h col add1 row add1 row add2 row add3 dout n dout n+ 1 dout m column address row address cle ce# we# ale re# i/ox r/b# trp * for t he c ommand 50h, a[3:0] in col add1 are valid address and a [7:4] are don?t c are tar
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 31 of 53 figure 22. pnand mode lbd ra ndom data operation (casdo) trc tr tc lr twhr twb tar trr trea busy 00h col add1 row add1 30h dout n dout n+ 1 05h e0h dout m col add2 row add2 row add3 col add1 col add2 dout m+1 column address row address column address cle ale i/ox we # r/b# ce# re# trp trhw figure 23. pnand mode register read using casdo in 8-bit mode tclr twhr trea 05h e0h col add1 col add2 column address cle ale i/ox we# r/b# ce# re# dout1 *dout2 * this timing diagram shows the 8-bit register read. for 16-bit register read, dout2 is not available tch
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 32 of 53 figure 24. pnand mode lbd read operation (with ce# don?t care) cle ale i/ox we# r/b# ce# twb busy column address row address re# 00h col add1 col add2 row add1 row add2 row add3 30h d out n dout n+1 t r dout m dout i/ox ce# re# tcea trea
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 33 of 53 figure 25. pnand mode sbd read operation (with ce# don?t care) cle ale i/ox we# r/b# ce# column address row address re# 00h col add1 row add1 row add2 row add3 twb busy d out n dout n+1 t r dout m d out i/ox ce# re# tcea trea
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 34 of 53 figure 26. pnand mode lbd page program operation twb 80h col add1 row add1 col add2 row add2 row add3 column address row address tprog twc tadl serial data input command din n din m 10 h 70h i/o0 1 up to m byte serial input program command m = 2112byte in 8-bit interface m = 1056 in 16-bit interface i/o0=0 successful pr ogram i/o0=1 error in program note: tadl is the time from we rising edge of final address cycle to the we rising edge of first data cycle read status command cle ale i/ox we# r/b# ce# re# twhr
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 35 of 53 figure 27. pnand mode s bd page program operation 80h col add1 row add1 row add2 column address row address tprog twc tadl serial data input command din n din m 10h 70h i/o 0 1 up to m byte serial input pr ogr am command m = 528 byte in 8-bit interface m = 264 byte in 16-bit interface i/o0=0 successful program i/o0=1 error in program read status command cle ale i/ox we# r/b# ce# re# row add3 twb
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 36 of 53 figure 28. pnand mode lbd page program op eration with random data input (casdi) twb 80h col add1 row add1 col add2 row add2 row add3 column address row address tprog twc serial data input command din j din k 70h i/o0 read status command tadl din n din m col add2 col add1 10h serial input program command random data input command column address serial input 85h cle ale i/ox ce# we# re# r/b# twhr *random programming (casdi) to endpoint is only supported during logical nand em ulation (lna mode) of lbd device. partial page programming is not supported figure 29. pnand mode register write usin g casdi in 8-bit mode tadl din1 *din2 col add1 random data input command serial input 85h cle ale i/ox ce# we# re# r/b# col add2 * this timing diagram shows the 8-bit register write. for 16-bit register write, din2 should not be available twc
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 37 of 53 figure 30. pnand mode lbd page progr am operation (with ce# don?t care) twb 80h col add1 row add1 col add2 row add2 row add3 column address row address tprog twc tadl serial data input command din n din m 10h 70h i/o0 1 up to m byte serial input pr ogr am command m = 2112 byte in 8-bit interface m = 1056 byte in 16-bit interface i/o0=0 successful program i/o0=1 error in program note: tadl is the time from we rising edge of final address cycle to the we rising edge of first data cycle read status command cle ale i/ox we# r/b# ce# re# twhr ce# we# tcs twp tch
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 38 of 53 figure 31. pnand mode sbd page pr ogram operation (with ce# don?t care) 80h col add1 row add1 row add2 column address row address tprog twc tadl serial data input command din n din m 10h 70h i/o 0 1 up to m byte serial input program command m = 528 byte in 8-bit interface m = 264 byte in 16-bit interface i/o0=0 successful program i/o0=1 error in program read status command cle ale i/ox we# r/b# ce# re# row add3 twb ce# we# tcs twp tch
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 39 of 53 figure 32. pnand mode block erase operation twc 60h row add2 row add1 row add3 d0h 70h i/o 0 busy auto block er ase setup command row address read status command i/o0=0 successful erase i/o0=1 error in erase erase command twb tbers cle ale i/ox r/b# re# we# ce# figure 33. pnand mode multi-blocks (up to 4) erase 60 h row add2 row add1 row add3 d0h 70h i/o 0 busy auto block erase setup command row address r e ad s tatus command i/o 0= 0 successful erase i/o0=1 error in erase er a se c o mm a nd twb tbers cle ale i/ox r/b# re# we# ce# tw c 60h row add2 row ad d 1 row ad d 3 d0h auto block erase setup command row address erase command 4 th block erase 1 st block erase 2 nd and 3 rd blo ck er a se note: the multi-block erase can support up to 4 blocks erase
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 40 of 53 figure 34. pnand mode read id operation 90h cle ale we# i/ox re# ce# tar trea byte 0 read id command address 1cycle byte 1 byte 2 byte 3 byte 4 byte 5 byte 0 ? byte 5 are the values of registers of pnad_rd_id0 to pnand_rd_id5. can up to six bytes 00h figure 35. pnand mode read id2 operation 91h 00h cle ale we# i/ox re# ce# tar trea ext_id read id command address 1cycle
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 41 of 53 figure 36. pnand mode reset operation twb trst cle ce# we # r/ b # i/ox ffh table 12. spi mode parameters parameter description min max units f op operating frequency 0 26 mhz t cyc cycle time 38.5 ? ns t lead enable lead time 19.23 ? ns t lag enable lag time 19.23 ? ns t sckh clock high time 17.33 ? ns t sckl clock low time 17.33 ? ns t su data setup time (inputs) ? 7 ns t h data hold time (inputs) ? 7 ns t v data valid time, after enable edge ? 18 ns t ho data hold time, after enable edge 0 ? ns
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 42 of 53 figure 37. spi timing diagram t cyc t sckh t sckl t lead t su t h t lag t v t ho ss# sck miso mosi (msb) bit-7 in bit-6 in (lsb) bit-0 in (msb) bit-7 out bit-6 out (lsb) bit-7 out note note: not defined but normal msb of character just received t ho table 13. pi2c interface standard mode parameters parameter description min max units f operating frequency 0 82 khz t buf bus free time (between stop and start conditions) 4.7 ? s t hd:sta hold time after (repeated) start condition. after this period the first clock is generated 4.0 ? s t su:sta repeated start condition setup time 4.7 ? s t su:sto stop condition setup time 4.0 ? s t hd:dat data hold time 0?ns t su:dat data setup time 250 ? ns t timeout detect clock low timeout na ms t low clock low period 4.7 ? s t high clock high period 4.0 ? s t low:sext cumulative clock low extend time (slave device) na ms t r rise time ? 1000 ns t f fall time ?300ns
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 43 of 53 other p-port timings drq# min pulse width (t dpw ) : the minimum duration that drq# is deasserted following a drq acknowledgement (clear of dmaval) is 110 ns in async mode or five p-port clock (clk) cycles in sync mode. same register writ e-to-read holdoff (t wrho ) : a read of a particular register must wait for a holdoff period following a write operation to that same regist er address to ensure that valid updated data is read. in async mode, this holdoff time is 150 ns. in sync mode, this holdoff time is seven p-port clock (clk) cycles. register update-to-read holdoff (t urho ) : same status registers are updated as side effect from accesses to other registers. for example, clearing the dmaval field automatically clears the associated endpoint buffer bit within the drq status register. a holdoff time must elapse from the first register access before the update is reflected in a subsequent read operation. this holdoff time is identical to the t wrho . s port interface ac timing parameters sd/mmc/mmc+ timing parameters for all conditions, sd/mmc data is driven and sampled on the rising edge of sd_clk. note that ce-ata electrical and timing parameters are equivalent to mmc. table 14. pi2c interface fast mode parameters parameter description min max units f operating frequency 0 312 khz t buf bus free time (between stop and start condition) 1.3 ? s t hd:sta hold time after (repeated) start condition. after this period the first clock is generated 0.6 ? s t su:sta repeated start condition setup time 0.6 ? s t su:sto stop condition setup time 0.6 ? s t hd:dat data hold time 00.9ns t su:dat data setup time 100 ? ns t timeout detect clock low timeout na ms t low clock low period 1.3 ? s t high clock high period 0.6 ? s t low:sext cumulative clock low extend time (slave device) na ms t r rise time ?300ns t f fall time ?300ns figure 38. pi2c timing diagram t f t r t hd;sta t low t hd;dat t su;dat t high t su;sta t buf t su;sto t hd;sta ssrs p sda scl 70% 30% 50% 50% 50% 70% 30%
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 44 of 53 figure 39. sd/mmc+ timing waveform ? all modes sd_cmd/ sd_d0-d3 output sd_clk tsdclk tsdclkl sd_cmd/ sd_d0-d3 input tsdclkh tsdoh tsdos tsdih tsdis tsdckhz tsdcklz table 15. common timing parameters fo r sd/mmc+ ? during identification mode parameter description min max units sdfreq sd_clk interface clock frequency 0 400 khz t sdclk clock period 2.5 ? s t sdclkh clock high time 1.0 ? s t sdclkl clock low time 1.0 ? s table 16. common timing parameters for sd/mmc+ ? during data transfer mode parameter description min max units sdfreq sd_clk interface clock frequency 5 48 mhz t sdclk clock period 20.8 200 ns t sdclkod clock duty cycle 40 60 % t sclkr clock rise time ? 3 ns t sclkf clock fall time ?3ns table 17. timing parameters for sd ? all modes parameter description min max units t sdis input setup time 4 ? ns t sdih input hold time 2.5 ? ns t sdos output setup time 7 ? ns t sdoh output hold time 6 ? ns t sdckhz clock to data high z ? 18 ns t sdcklz clock to data low z 3 ? ns
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 45 of 53 reset and standby timing parameters the arroyo reset mechanism is described in this section. the standby mode is also described. sleep time (t slp ) : the maximum time from deassertion of wakeup to when arroyo enters low power state (sleep mode) is 1 ms. wakeup time (t wu ) : the minimum time from assertion of wakeup pin (or initial power on with wakeup high) to when any register operation is conduct ed is 1 ms if an external clock is present, or 5 ms if a crystal is used. the cy_an_mem_pwr_magt_stat.wakeup field can only be polled after wakeup time following reset deassertion or wakeup assertion. minimum reset# pulse width (t rpw ) : 5 ms when a crystal is used as clock or 1 ms when an external clock is used. minimum wakeup pulse width (t wpw ) : 5 ms. minimum high on re set# and wakeup (t rh , t wh ) : the wakeup and reset# pins must be held high for a minimum of 5 ms. reset recovery time (t rr ) : a minimum 1 ms reset recovery time must be allowed before arroyo registers can be accessed for read or write. table 18. timing parameters for mmc+ ? all modes parameter description min max units t sdis input setup time 4 ? ns t sdih input hold time 4 ? ns t sdos output setup time 6 ? ns t sdoh output hold time 6 ? ns t sdckhz clock to data high z ? 18 ns t sdcklz clock to data low z 3 ? ns figure 40. reset and standby timing diagram reset# resetout wakeup firmware init complete mandatory reset pulse standby mode hard reset high-z firmware init complete mandatory reset pulse firmware init complete cy_an_mem_pmu_update.uvalid bit is set to ?1? cy_an_mem_pmu_update.uvalid bit is set to ?0? cy_an_mem_pmu_update.uvalid bit is set to ?0? tslp trpw twpw vdd (core) core power-down vddq (i/o) xtalin xtalin up & stable before wakeup asserted twh trh
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 46 of 53 table 19. reset and standby timing parameters parameter description conditions min max units t slp sleep time ?1ms t wu wakeup time from standby mode clock on xtalin 1 ? ms crystal on xtalin-xtalout 5 ? ms t wh wakeup high time 5 ? ms t wpw wakeup pulse width 5 ? ms t rh reset# high time 5 ? ms t rpw reset# pulse width clock on xtalin 1 ? ms crystal on xtalin-xtalout 5 ? ms t rp reset# recovery time 1 ? ms figure 41. ac test loads and waveforms (except sd and mmc, sd and mmc are comply wi th the sd/mmc specification)
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 47 of 53 ordering information for ordering information, contact your local sales representat ive. for more information, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products . table 20. device ordering information ordering code package type clock input frequencies (mhz) cywb0320abx-fdxi 81-pin wlcsp (pb-free) 26 CYWB0320ABX-FDXIT 81-pin wlcsp (pb-free) 26 cywb0321abx-fdxi 81-pin wlcsp (pb-free) 19.2, 26 cywb0321abx-fdxit 81-pin wlcsp (pb-free) 19.2, 26 ordering code definitions x = blank or t blank = tube; t = tape and reel temperature range: i = industrial pb-free package type: fd = 81-pin wlcsp pin count part number family code technology code: wb = west bridge company id: cy = cypress wb cy 03 xxx - fd t t x xx
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 48 of 53 package diagram figure 42. astoria 81-pin wlcsp (3.91 3.91 0.55 mm) fn81b package outline, 001-45618 h g f e d c b a 1 2 3 4 5 6 7 8 9 j 123456789 h g f e d c b a j top view bottom view side view 001-45618 *c
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 49 of 53 acronyms document conventions units of measure acronym description ce chip enable esd electrostatic discharge i/o input/output lsb least significant bit msb most significant bit oe output enable re read enable spi serial peripheral interface usb universal serial bus we write enable wlcsp wafer level chip scale package symbol unit of measure c degree celsius ma milliampere mhz megahertz a microampere f microfarad s microsecond w microwatt ms millisecond mv millivolt mw milliwatt ns nanosecond ppm parts per million pf picofarad vvolt wwatt
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 50 of 53 errata this section describes the errata for west bridge arroyo usb and mass storage perip heral controller, cywb 0320abx-fdxi. details include errata trigger conditions, scope of impact, av ailable workarounds, and silicon revision applicability. contact your local cypress sales re presentative if you have questions. part numbers affected arroyo qualification status product status: in production arroyo errata summary the following table defines the errata applicability to available a rroyo family devices. an ?x? indicates that the erratum pert ains to the selected device. 1. p-port sram mode fails if oe and ce are not asserted simultaneously problem definition when arroyo is configured to use sram for p-port interface, oe should be asserted simu ltaneously with ce. if this is not possib le, oe should be asserted prior to ce. parameters affected data can be dropped when external processor reads the arroyo through sram interface. trigger condition(s) when arroyo p-port is configured in sram mode and if oe and ce don?t happen at the same time. scope of impact nil workaround the workaround available at this time include asserting oe and ce at the same time and asserting oe prior to ce. fix status nil. part number package type operating range cywb0320abx-fdxi 81-pin wlcsp industrial items cywb0320abx-fdxi revision fix status 1. p-port sram mode fa ils if oe and ce are not asserted simultaneously. [x] a ?
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 51 of 53 errata this section describes the errata for west bridge arroyo u sb and mass storage peripheral controller, cywb0321abx-fdxi. details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability. contact your local cypress sales re presentative if you have questions. part numbers affected arroyo qualification status product status: in production arroyo errata summary the following table defines the errata applicability to available a rroyo family devices. an ?x? indicates that the erratum pert ains to the selected device. 1. p-port pspi mode fails u-port to p-port transfer after wake up from standby mode problem definition when arroyo is configured to use spi for pr ocessor-port (p-port) interface, transfers from u-port to p-po rt may intermittently fail after wakeup from standby mode. parameters affected intermittent failure in u-po rt to p-port transfer after wakeup from standby. trigger condition(s) the condition occurs when arroyo is configur ed for pspi mode and wakes up from standby mode. scope of impact when arroyo is configured to use spi for pr ocessor-port (p-port) interface, transfers from u-port to p-po rt may intermittently fail after wakeup from standby mode. workaround sdk version 1.0 or later provides the software workaround for th is issue. the workaround requires using version 1.0 or later of the sdk for the system software development. the workaround fixes the intermittent failure as described in probl em definition. however, the workaround cause wakeup time (fr om standby mode) to increase. this duration increase depends upo n the system configuration as listed in the following table: this errata only affects arroyo when the p-port is configured for spi mode. fix status fixed in sdk version 1.0 or later. part number package type operating range cywb0321abx-fdxi 81-pin wlcsp industrial items cywb0321abx-fdxi revision fix status 1. p-port pspi mode fails u-port to p-port transfer after wake up from standby mode. [x] a fixed in sdk in version 1.0 or later arroyo system configuration additional wakeup time (from standby mode) using external crystal 5 ms using external oscillator 1 ms firmware image is loaded from eeprom (through i2c ? ) > 250 ms depending on the firmware image size and the i 2 c frequency
cywb0320abx-fdxi cywb0321abx-fdxi document number: 001-57458 rev. *g page 52 of 53 document history page document title: cywb0320abx-fdx i/cywb0321abx-fdxi, west bridge ? : arroyo usb and mass storage peripheral controller document number: 001-57458 revision ecn orig. of change submission date description of change ** 2846580 shin / aesa 01/12/2010 new data sheet. *a 2902575 stvc 03/31/2010 updated pin assignments (updated ta b l e 4 ). updated ac timing parameters (added pcram non multiplexing asynchronous mode subsection). changed status from advance to final. updated links in sales, solutions, and legal information . *b 3207801 anop 03/28/2011 updated pin assignments (in table 4 , changed r/b# from ?i? to ?o? in the ?i/o' column corresponding to ?pnand?, changed ?a7 or sda? to ?a6 or sda? in the ?pin description? column corresponding to ball h1, changed ?a6 or scl? to ?a5 or scl? in the ?pin description? column corresponding to ball f2, changed sd_clk from ?i/o? to ?o? in the ?i/o' column corresponding to 's-port interface?.). *c 3499405 rskv 01/17/2012 updated title to read as ?cywb0320abx-fdxi/cywb0321abx-fdxi, west bridge ? : arroyo usb and mass storage peripheral controller?. updated features . updated functional overview (updated the subsection processor interface (p-port) (description), updated the subsection clocking (description, updated table 1 and added table 2 ). updated pin assignments (updated ta b l e 4 and added table 5 , updated caption of figure 3 and added figure 4 ). updated ac timing parameters (added ta b l e 1 2 and figure 37 ). added ordering information . replaced arroyo-ii with arroyo across the document. updated in new template. *d 3539329 rskv 03/01/2012 moving to external web. removed the tag ?company confidential? from the header. revised package diagram spec. *e 3878676 rskv 01/21/2013 no technical updates. completing sunset review. *f 3978102 rskv 04/22/2013 added acronyms and units of measure . added errata . added errata . *g 4072903 rskv 07/22/2013 added errata footnotes (note 1, 2, 10). updated pin assignments : added note 1 and referred the same note in ?sram interface? column in table 4 . added note 2 and referred the same note in ?spi? column in ta b l e 5 . updated ac timing parameters : updated p port interface : updated asynchronous sram mode timing parameters : added note 10 and referred the same note in figure 12 . updated in new template.
document number: 001-57458 rev. *g revised july 22, 2013 page 53 of 53 west bridge is the registered trademark and astoria, antioch, and slim are trademarks of cypress semiconductor corporation. all products and company names mentioned in this document may be the trademarks of their respective holders. cywb0320abx-fdxi cywb0321abx-fdxi ? cypress semiconductor corporation, 2010-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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